Even the Systeme Internationale (SI) unit of the Volt is defined by a superconductor
integrated circuit. HYPRES, Inc. (Elmsford, NY) currently offers commercial products
based on superconductor integrated circuits, packaged with a small mechanical refrigerator
to provide temperature regulation, allowing this standard volt to be reproduced anywhere in
the world with quantum mechanical accuracy. Simply put, these are applications that cannot
be performed with any other technology; therefore the motivation to accept the unique
character of cryogenic operation is strong. As a consequence, these applications have driven
the state of the art in cryopackaging to the point where all cryogenics have become invisible
to users of such products.
5.1.3 Emerging Applications – Software Defined Radio
As the ‘cryophobia’ associated with superconductor microelectronics is overcome, the range
of possible applications continues to widen. In communications, dispersion-free, ultra-high
Q superconductor microwave filters for cellular base stations are today offered from several
companies in the United States, Europe, and Japan. Close to a thousand such units have
been purchased and installed around the United States, with orders pending from major
carriers in Europe. The use of superconductor material allows the very high Qstobe
maintained, while microminiaturizing the overall filter size. The ultra-sharp filter ‘skirts’
that result enable increased channel selectivity and, with a cooled LNA, yield increased
sensitivity as well.
Recently, wireless telephony has been shifting from voice/narrowband data to wideband
data, along with demands for significant increases in capacity. These have become the
industry’s major drivers, with the major obstacles becoming air interface compatibility
and bandwidth allocation. An increasingly embraced solution to surmount these obstacles
lies in the concepts of software radio [5]. However, realization of software radio systems
Superconductor Microelectronics: A Digital RF Technology for Software Radios 131
Table 5.1 Demonstrated RSFQ digital circuit performance
Circuit type Circuit metric(s) Circuit type Circuit metric(s)
Toggle flip-flop 144 GHz 2-bit counter 120 GHz
4-bit shift register 66 GHz l-kbit shift register 19 GHz
6-bit flash ADC 3 ENOB
a
at 20 GHz 6-bit transient digitizer
with 6 £ 32 bit on-chip
memory buffer
16 GS/s
14-bit high-resolution
ADC (2 MHz)
14 ENOB and 2100
dBc SFDR
b
18-bit DAC Fully functional at
low speed
1:8 demultiplexor
(synchronous)
20 Gb/s 1:2 demultiplexor
(asynchronous)
95 Gb/s
1-bit half-adder 23 GHz 2-bit full-adder 13 GHz
8 £ N bit serial
multiplier
16 GHz 14-bit digital comb filter 20 GHz
128-bit autocorrelator 16 GHz Time-to-digital
converter
31 GHz
a
ENOB, effective number of bits.
presents a host of challenges – chief among them the unprecedented requirement on analog-
to-digital converter (ADC) performance [6]. This is the area where superconductor micro-
electronics represents an emerging solution. With demonstrated ADC, DAC, and DSP
components, this technology may well become a key enabling technology for software
radio [7]. Table 5.1 summarizes the performance already achieved with such superconduct-
ing devices to date. Unlike commercial systems, which are primarily cost/performance-
driven, defense applications tend to be primarily performance driven, with cost as a close
second. In addition, military radio requirements are far more demanding than those for
commercial systems.
5.2 Rapid Single Flux Quantum Digital Logic
By now the reader may be wondering why a digital superconductor IC technology has not
already been established. In fact, there were two large digital superconductor programs – one
that ran at IBM from 1969 to 1983 and another in Japan from 1981 to 1990. Rather than
relying directly on quantized bundles of magnetic flux as bits, those efforts (and others at the
time) attempted to use the voltage state of the JJ as a ‘1’ and the superconducting state as a
‘0’. Many fully functional circuits were demonstrated, culminating with a 1 GHz 4-bit micro-
processor by NEC [8]. However, it was this choice of logic convention which ultimately led
to the conclusion of the program. A reset effect called ‘punchthrough’ limited the speed of
operation to just a few GHz. In contrast, very large scale integration (VLSI) RSFQ circuits
should operate up to 250 GHz. Power consumption was another issue. A typical latching gate
dissipated about 3 pW. Although this sounds small, RSFQ technology dissipates only one
tenth of this, at 0.3 pW/gate. The need to distribute an AC power supply was also a problem
and made timing issues extremely complex.
5.2.1 Circuit Characteristics
5.2.1.1 Circuit Structures
In RSFQ circuits, it is not a static voltage level, but the presence or absence of quantized
magnetic flux (fluxons) that represents information bits. The basic RSFQ structure is a super-
conducting ring that contains one Josephson junction plus a resistive shunt outside it (see
Figure 5.4).
Suppose a current is already a circulating around the loop, supporting one fluxon. At a certain
critical current level (about 100 mA for typical designs), additional DC current across the loop
causes the fluxon to be ejected, with the Josephson junction acting as a briefly opened exit.
Rather than use the escaping flux directly, RSFQ relies on the fact that the movement of a
fluxon into or out of this loop induces a very short voltage pulse (known as an ‘SFQ pulse’, for
single flux quantum) across the junction. If the Josephson junction were a square, 1 mmona
side, this SFQ pulse would be <1 ps long and 2 mV in amplitude. The SFQ pulses become
narrower and greater in amplitude as the junctions decrease in area but, because their
magnetic flux is quantized, the voltage–time product of the pulse always remains the
same: 2 mV-ps, i.e. 2 £ 10
215
Wb. The energy consumed each time an SFQ pulse passes
through a junction is just the circulating current of about 100 mA times the amount of flux F
0
,
or only ~2 £ 10
219
J.
These SFQ pulses are used to form RSFQ digital logic gates composed of only a few basic
Software Defined Radio: Enabling Technologies132
circuit structures. These building blocks allow the generation, transfer, storage, and condi-
tional routing, or ‘switching’, of SFQ pulses. Shown in Figure 5.5, the three basic structures
include an active transmission stage (JTL or Josephson transmission line), the storage loop,
and the decision making pair (or comparator).
5.2.1.2 Fabrication and Packaging
RSFQ integrated circuits are made with standard semiconductor manufacturing equip-
ment; however, there are many fewer mask layers (typically about ten) and the actual
processing involves much less complex depositions [9,10]. Because RSFQ logic is an all-
Superconductor Microelectronics: A Digital RF Technology for Software Radios 133
Figure 5.4 Physical realization of a resistively shunted Josephson junction
Figure 5.5 The three basic structures of RSFQ logic
thin-film technology, there are no doping profiles to calculate, no high temperature drive-
ins, no epitaxial growths, or chemical vapor depositions. These differences are expected
to translate directly into reduced costs in the large scale manufacture of RSFQ electro-
nics.
Architectures containing both front end analog circuitry, as well as digital processing
blocks, are fundamental SDR requirements. This configuration presents extraordinary diffi-
culties for semiconductors, due to ‘crosstalk’–problems of interference between the analog
and digital sections of the same chip. Because of the unique reliance on single quanta of
magnetic flux to convey information, RSFQ are inherently more immune to this sort of
crosstalk.
The RSFQ technology also has a clear path to extend performance. Unlike semiconductor
devices, the speed of RSFQ ICs comes from inherent physical phenomena, not ultra-small
scaling. This means that existing lithography techniques can be employed and, more impor-
tantly, existing equipment can fabricate circuitry that surpasses conventional limits of perfor-
mance. Because RSFQ logic uses the lossless ballistic transmission of digital data fluxons on
microstriplines near the speed of light, the wire up nightmare that silicon designers face is
substantially reduced. This scenario also allows the full speed potential of individual gates to
be realized.
Other features of this technology that make it suitable for growth into the traditional market
include its compatibility with existing IC packaging techniques. These include compatibility
with optical (fiber) signal input and output, a maturing multichip module (MCM) technology
with multi-Gb/s digital data transfer between chips, and simple interface circuits to convert to
and from both ECL logic and CMOS logic levels.
5.2.2 Example RSFQ Logic Gate – RS Flip Flop
To transfer SFQ pulses as information bits, a clock may be used to provide a steady stream of
timing pulses (one per clock cycle), such that the presence of a data pulse within the clock
cycle denotes a logic (1), while the absence of one denotes a logic (0). Combinations of
Josephson junctions can then be interconnected to achieve SFQ pulse fan-in and fan-out and
create a variety of logic structures. Although all common binary logic primitives (like AND,
Software Defined Radio: Enabling Technologies134
Figure 5.6 Basic building blocks of an RSFQ gate
OR, or XOR) can be fashioned, it is often more convenient to create gate macros directly
rather than from lower logic primitives. This technique maximizes speed and minimizes
junction count. The operation of an RSFQ reset–set flipflop gate provides a simple example
(see Figure 5.6).
If a set pulse arrives, J1 transmits it into the quantizing inductance loop, where it becomes
trapped as a circulating current – the 1 state. This current biases J3, so that when a clock/reset
pulse arrives at the gate, it causes J3 to transmit the stored fluxon to the output, thus resetting
the flipflop to the 0 state. Alternatively, if no set pulse input has occurred during the clock
period and a clock/reset pulse arrives, the unbiased J3 cannot transmit the pulse and J2 is
forced to let the fluxon escape the circuit, so no pulse appears at the output.
5.2.3 RSFQ Data Converters
5.2.3.1 Analog to Digital Converters
The quantum precise periodic transfer function of the superconducting quantum interfer-
ence device (SQUID) makes superconductor circuits an excellent choice for data conversion
from a continuous time to a discrete time format [11]. Figure 5.7 shows a block diagram and a
chip photo of an RSFQ ‘high resolution’ ADC based on a phase modulation/demodulation
architecture [12].
This superconductor ADC design is especially linear, because the quantization thresholds
are set by a ratio of fundamental physical constants (h/2e) in the SQUID in the front end. This
leads to an enhanced spurious free dynamic range (SFDR) in comparison to semiconductor
ADCs, whose thresholds are set by the matching of device characteristics. Common perfor-
mance metrics for ADCs are the SINAD and the SFDR.
2
SINAD is a signal-to-noise and
Superconductor Microelectronics: A Digital RF Technology for Software Radios 135
Figure 5.7 Phase modulation/demodulation ADC: block diagram and chip photograph
2
These metrics are described generally in Chapter 2, and, in the context of ADCs, in Chapter 4.
distortion measurement, and represents the dynamic range of the signal with respect to all
digitization artefacts. SFDR is the spurious free dynamic range, reflecting the linearity of the
ADC process by indicating the ratio of signal to the highest spurious signal in the Nyquist
band.
Demonstrated performance for the first HYPRES RSFQ ADC (shown in Table 5.2) is a
SINAD of 58.2 dB (9.4 effective bits) and an SFDR of 278.7 dBc at 100 MS/s Nyquist rate
sampling. The same chip also provides 14.5 effective bits (a SINAD of 89.1 dB) with an
SFDR of 2100 dBc for a DC to 2.3 MHz band at 5.5 MS/s.
The circuit consists of two major parts: a differential code, front end quantizer and a digital
decimation low pass filter. The front end is composed of an analog phase modulator and a
digital phase demodulator. The phase modulator consists of a single-junction SQUID, biased
by a DC voltage from a special voltage source, which is stabilized by an internal clock
frequency. The phase demodulator consists of a time-interleaved bank of race arbiters
(SYNC) followed by a thermometer to binary encoder (DEC).
In order to obtain a binary differential code from the thermometer code outputs of the
synchronizer bank, the encoder block adds up these outputs and subtracts N/2 each clock
period. The differential code from the output of the front end is passed to a digital decimation
low pass filter (DSP), which uses a standard cascaded integrator comb (CIC) architecture with
two integration stages. The first integration stage restores the signal from the differential
code, and the second one provides first-order low pass filtering.
The dynamic resolution, or effective number of bits (ENOB), of this ADC is determined by
the input signal bandwidth (BW), the internal clock frequency f
clk
, and the number of synchro-
nizer channels N and is given [13] by
ENOB ¼ log
2
ðNf
clk
=
p
BWÞ 1 1=2 log
2
ðf
clk
=2BWÞð1Þ
The first term in this formula accounts for a slew rate limit (i.e. limited by the signal
derivative), while the second one comes from standard oversampling gain. Here, the BW
is assumed to be half the output sampling rate (i.e. at the Nyquist limit). Therefore, (1) gives a
bandwidth-to-resolution trade-off ratio of 1.5 bits per octave, as expected for a first-order
oversampling ADC.
5.2.3.2 Digital-to-Analog Converters
A number of different so-called ‘programmable Josephson voltage standards’ have been
proposed [14,15]. Each of these designs consists of a superconductor digital-to-analog
converter (DAC) based on the properties of flux quantization. When a quantized SFQ
Software Defined Radio: Enabling Technologies136
Table 5.2 Demonstrated RSFQ ADC performance
Sample rate MS/s ENOB bits SINAD dB SFDR dBc Input MHz
100 9.4 58.2 278.7 DC to 50
25 12.6 77.8 291.0 DC to 10
5.5 14.5 89.1 2100 DC to 2.3
pulse is used to represent digital data, the AC Josephson effect
3
(i.e. frequency-to-voltage
relationship) gives access to a method for directly transferring back into the analog domain.
The fact that a SFQ DAC uses the same fundamental physics that define the unit of the Volt
has some profound consequences [16]. For instance, any instantaneous voltage generated by
the DAC will be precise to the accuracy of the definition of the Volt. Further, every waveform
cycle generated will be exactly the same, with quantum precision. The small time constants
associated with Josephson junctions may make it possible to extend such performance to
many GHz, although very large arrays of JJs may be necessary to achieve useful levels of
output voltages suitable to drive high power amplifiers (HPAs).
An RSFQ DAC design based around a voltage multiplier (VM) block was first shown by
Semenov [17]. This DAC (seen in Figure 5.8) uses each bit of an N-bit RSFQ digital word to
drive an RSFQ digital to frequency converter (DFC) (sometimes noted as ‘SD’).
A DFC is designed to output a stream of SFQ pulses at a frequency that is proportional to
its reference clock frequency, only when the bit value at its input is ‘1’. By arranging a series
of N DFCs with reference frequencies f
N
that decrease as 2
2N
, one can effectively create a
binary weighted set. By switching different DFCs in and out of the series with the digital input
word, any of 2
N
combinations can be chosen. The VM is an inductively coupled SQUID chain
used to transform the DFC streams offlux quanta into time-averaged voltages, then sum them,
creating a corresponding output voltage with N-bit resolution. By updating the N-bit input
word periodically, at a rate slower than the slowest DFC reference frequency, one creates a
DAC. The voltage at the output of the DAC during a single sampling period is given by V
out
¼
MF
0
f
0
, where f
0
is a readout or sampling clock frequency, and M is the total number of SFQ
pulses driven through the VM by all the DFCs. The LSB of the output voltage is nF
0
f
0
, where
Superconductor Microelectronics: A Digital RF Technology for Software Radios 137
3
When using fluxons, F
0
, as data bits, a time-averaged voltage measurement serves as a direct measurement of the
bit rate according to the relation kVl ¼ F
0
/s, where the measurement accuracy is determined by the uncertainty limit
on the voltage measurement apparatus.
Figure 5.8 RSFQ DAC: block siagram and chip photograph
n is the number of stages in the smallest stage of the VM. The output dynamic range is
2
N
LSB, where N is the resolution of the DAC in bits.
Many bits of dynamic range are possible, because the initial reference clock can be very
high. The chip in this figure is a 22-bit DAC. Experimental results of an 8-bit design have
been shown. The differential nonlinearity (DNL) of the DAC is ,0.1 LSB. With the proper
microwave engineering of the VMs, a multi-GHz output rate (effective bandwidth) could be
achieved, while maintaining significant dynamic range. The update clock and output clock
are synchronized to prevent spikes during code transitions.
5.2.4 RSFQ Scaling Theory
The basic scaling laws for Josephson junctions in RSFQ circuits are well known [18]. The
junction fabrication process defines the thickness of the tunneling barrier d ~1–2 nm, which
in turn determines the critical current density J
c
, which is exponentially dependent on d. Once
J
c
is fixed, the primary constraint on the junction scale a is that the junction be large enough to
avoid thermal fluctuations, typically with I
c
. 100 mA for Nb circuits. For a large scale digital
integrated circuit, this constraint assures that the bit error rate is sufficiently small.
For RSFQ circuits, the high frequency performance is determined primarily by the width of
the SFQ pulse generated by a nonhysteretic Josephson junction (RC , L
J
/R). Because the
time-integral of the SFQ voltage pulse is F
0
¼ 2 mV-ps, the pulse height is roughly V
c
<
2I
c
R, and the pulsewidth is t < F
0
/2I
c
R [1]. By decreasing the scale of a Nb junction, the pulse
can be made narrower until around a < 0.3 mm, where V
c
< 4.8 mV and
t
< 0.4 ps. For
junction sizes a, above this limit, external shunt resistors are employed to ensure that (RC ,
L
J
/R).
Although JJs are the central elements of RSFQ circuits, they are not the only elements.
Equally important are inductors and resistors. These can also be scaled down in size in a
consistent way [19]. In this case, the speed of complex RSFQ circuits should scale with the
reciprocal pulse width 1/
t
. In particular, it is a rough rule of thumb that the maximum clock
frequency of a synchronous RSFQ circuit is approximately
Software Defined Radio: Enabling Technologies138
Table 5.3 RSFQ scaling theory
a
Quantity Transformation
Current I ! I
Voltage V ! V
a
Flux F ! F
Distance on chip Dx ! Dx/
a
Time delays Dt ! Dt/
a
Resistance R ! R
a
Capacitance C ! C/
a
2
Inductance L ! L
Junctions/area N ! N
a
2
Power/area P ! P
a
2
a
Scaling down by a factor of
a
, in regime where shunt
resistance is still needed
f
c
<
1
10
t
<
75 GHz
a½mm
; ð2Þ
where again this scaling relation should continue only down to a scale of 0.3 mm, for a
maximum limiting VLSI clock speed of about 250 GHz.
These scaling factors are summarized in Table 5.3. If all on-chip patterns are shrunk by
a factor
a
, then all times will be reduced by the same factor. This includes time delays
due to junctions, as well as time delays due to pulse propagation on transmission lines. So
even as the pulses become narrower, their relative timing in the circuit will remain
consistent.
5.3 Cryogenic Aspects
Naturally, superconductor RSFQ circuitry must be cooled for operation. The temperature of
operation is normally selected to be at about half the material’s superconducting transition
‘critical temperature’ (T
c
). For operating temperatures below about one-half T
c
, supercon-
ducting parameters are not strongly sensitive to small variations in temperature. For Nb
(T
c
¼ 9.23 K), operating at the boiling point of liquid helium (LHe) at one atmosphere
(4.2 K), meets this requirement. However, a closed cycle refrigerator (CCR or cryocooler)
with a 4.2–5Kfinal stage temperature is a more suitable platform for a commercial product
[20].
Cryocoolers are refrigerators in which mechanical work is performed on helium gas by first
compressing the gas under constant temperature conditions, and then allowing it to expand.
This action reduces the temperature of the gas, and can be repeated many times to achieve the
desired temperature. The efficiency of this thermodynamic process is called the ‘Carnot
efficiency’,
h
. For an ideal machine this relates the work done, W, to move a quantity of
heat, Q, from a low temperature to a warmer temperature and is defined as
h
;
Q
W
¼
T
cold
ðT
warm
2 T
cold
Þ
ð3Þ
In a real machine, there are actually some losses so
h
actually only defines a limit that can be
approached, and what is generally quoted is the fraction of the ideal case. The reciprocal of
this fraction is called the coefficient of performance (COP). At the present time, the COP for
4–5 K cryocoolers is about 4000 W/W. If the efficiencies of these cryocoolers could be
improved to about 5% of Carnot efficiency, then cryocoolers providing 0.25 W of cooling
capacity (as required by an RSFQ digital system),operating at temperatures of 4–5 K, would
consume 75 W (and have a mass of 30–40 kg). Figure 5.9 gives examples of current,
developing, and forecasted cryocooler profiles.
A cost-reliability goal for commercial cryocoolers has been suggested at US$1000–
10000 for a unit with a 2–10 year lifetime. Interestingly, the refrigeration power required
for an RSFQ system is only a fraction of a Watt, with the dominant heat load contributed
by heat leaks via radiation and conduction from the surrounding interface electronics,
rather than the heat from RSFQ chips themselves. The input power requirements of today’s
off the shelf CCRs are about 600–2000 W for 4.2 K, yielding 500 mW of refrigeration
power. For a typical RSFQ ADC system, a refrigerator might be needed that can cool a
minimum of 250 mW at 5 K. This cooling budget consists of 10 mW for the RSFQ chips
Superconductor Microelectronics: A Digital RF Technology for Software Radios 139
and 100 mW for the I/O heat load from a ~40 K stage to the ~5 K stage, with appropriate
design margins.
One of the main concerns frequently raised by potential users of cryogenic equipment is
that of reliability. When cryogenic refrigerators were initially introduced to the military and
commercial markets, they frequently failed after only several hundreds of hours of operation;
however, much progress has been made in this area. One approach to improve system lifetime
was the use of oil lubricated air-conditioning compressors. This is the type of CCR currently
used for HYPRES voltage standard products. A typical maintenance cycle is once per 3 years
to replace an oil absorber, or ‘scrubber’, that removes any contaminants in the oil that would
freeze out at low temperatures.
The other advance in reliability is the use of noncontacting suspension methods for the
piston in the cylinder. This approach has yielded mean time between failures (MTBF) of
several hundred thousand hours and is used in most higher temperature commercial cryo-
coolers (e.g. in military and civilian products for cooling infrared (IR) imaging systems). This
is the most likely candidate to be adapted for a low temperature superconductor SDR product
platform.
5.4 Superconductor SDR for Commercial Applications
5.4.1 Superconductors in Wireless Communications
In recent years, commercial wireless communication technology has been a growth area for
both voice and data transfer. Already, most wireless systems are implemented digitally, and
Software Defined Radio: Enabling Technologies140
Figure 5.9 Representative generations of closed-cycle refrigerators
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